1. Field of the Invention
The invention relates generally to the field of programmable logic devices (PLD's) and field-programmable gate arrays (FPGA's). The invention relates more specifically to the problem of routing bus signals into and through user-programmable devices.
2a. Cross Reference to Related Applications
The following U.S. patent applications are assigned to the assignee of the present application, are related to the present application and whose disclosures are incorporated herein by reference:
(A) Ser. No. 07/429,125 filed Oct. 30, 1989 by Om P. Agrawal et al., and entitled PROGRAMMABLE GATE ARRAY WITH IMPROVED INPUT/OUTPUT STRUCTURE (said application being a divisional of Ser. No. 07/394,221 filed Aug. 15, 1989 and issued May 18, 1993 as U.S. Pat. No. 5,212,652), now U.S. Pat. No. 5,233,539;
(B) Ser. No. 07/442,528 filed Nov. 27, 1989 by Om P. Agrawal et al., and entitled PROGRAMMABLE GATE ARRAY WITH IMPROVED LOGIC BLOCK, now U.S. Pat. No. 5,260,881;
(C) Ser. No. 07/538,211 filed Jun. 14, 1990 by Om P. Agrawal et al., and entitled IMPROVED INTERCONNECT STRUCTURE FOR PROGRAMMABLE LOGIC DEVICE, now U.S. Pat. No. 5,255,203;
(D) Ser. No. 07/514,297 filed Apr. 25, 1990 by Om P. Agrawal et al., and entitled PROGRAMMABLE GATE ARRAY WITH LOGIC CELLS HAVING SYMMETRICAL INPUT/OUTPUT STRUCTURES, now U.S. Pat. No. 5,231,588;
(E) Ser. No. 07/924,267 filed Aug. 3, 1992 by Om P. Agrawal, and entitled A MULTIPLE ARRAY PROGRAMMABLE LOGIC DEVICE WITH A PLURALITY OF PROGRAMMABLE SWITCH MATRICES, now abandoned;
(F) Ser. No. 07/924,685 filed Aug. 3, 1992 by Om P. Agrawal et al., and entitled ARCHITECTURE OF A MULTIPLE ARRAY HIGH DENSITY PROGRAMMABLE LOGIC DEVICE WITH A PLURALITY OF PROGRAMMABLE SWITCH MATRICES, now U.S. Pat. No. 5,457,409;
(G) Ser. No. 07/924,201 filed Aug. 3, 1992 by Om P. Agrawal et al., and entitled FLEXIBLE SYNCHRONOUS/ASYNCHRONOUS CELL STRUCTURE FOR A HIGH DENSITY PROGRAMMABLE LOGIC DEVICE, now U.S. Pat. No. 5,489,857;
(H) Ser. No. 08/012,573 filed Feb. 1, 1993 by Om P. Agrawal et al., and entitled PROGRAMMABLE GATE ARRAY WITH IMPROVED INTERCONNECT STRUCTURE, now U.S. Pat. No. 5,359,536; and
(I) Ser. No. 08/025,551 filed Mar. 3, 1993 by Om P. Agrawal et al., and entitled PROGRAMMABLE GATE ARRAY WITH IMPROVED INTERCONNECT STRUCTURE, INPUT/OUTPUT STRUCTURE AND CONFIGURABLE LOGIC BLOCK.
2b. Cross Reference to Related Patents
The following U.S. patent(s) are assigned to the assignee of the present application, are related to the present application and their disclosures are incorporated herein by reference:
(A) U.S. Pat. No. 5,015,884 issued May 14, 1991 to Om P. Agrawal, et al, and entitled, MULTIPLE ARRAY HIGH PERFORMANCE PROGRAMMABLE LOGIC DEVICE FAMILY;
(B) U.S. Pat. No. 5,151,623 issued Sep. 29, 1992 to Om P. Agrawal, and entitled, PROGRAMMABLE LOGIC DEVICE WITH MULTIPLE, FLEXIBLE ASYNCHRONOUS PROGRAMMABLE LOGIC BLOCKS INTERCONNECTED BY A HIGH SPEED SWITCH MATRIX; and
(C) U.S. Pat. No. 5,185,706 issued Feb. 9, 1993 to Om P. Agrawal, et al, and entitled, PROGRAMMABLE GATE ARRAY WITH LOGIC CELLS HAVING CONFIGURABLE OUTPUT ENABLE; and
(D) U.S. Pat. No. 5,212,652 issued May 18, 1993 to Om P. Agrawal et al., and entitled PROGRAMMABLE GATE ARRAY WITH IMPROVED INTERCONNECT STRUCTURE;
3. Description of the Related Art
The below disclosed invention covers two, apparently unrelated areas: (1) user-programmable devices and (2) board-level re-design. These areas (1)-(2) will be discussed individually by way of background; and then the cross-link between the two areas will become apparent as the invention is unveiled.
3a. User Programmable Devices
A variety of user-programmable devices (UPD's) are now available in the market. UPD's first became popular with the introduction field-programmable logic array devices (FPLA's) and programmable array-logic devices (PAL's) such as the Advanced Micro Devices 22V10. In these early devices, users were able to program logic functions into already-manufactured and packaged integrated circuit chips (IC's) by blowing addressable fuses.
A more sophisticated class of user-programmable devices (UPD's) emerged with the introduction of the XC2000 and XC3000 families of field-programmable gate array devices by Xilinx Inc. of San Jose, Calif. A description of the XC2000 series, as well as related programmable logic device art, can be found in THE PROGRAMMABLE GATE ARRAY DESIGN HANDBOOK, First Edition, published by Xilinx, pages 1-1 through 1-31. The architecture for the XC3000 family is provided in a technical data handbook published by Xilinx entitled XC3000 LOGIC CELL ARRAY FAMILY, pages 1-31. Each of these Xilinx publications is incorporated by reference in this application as providing a description of the prior art.
The prior art in programmable gate arrays is further exemplified by U.S. Pat. Nos. 4,642,487; 4,706,216; 4,713,557; and 4,758,985; each of which is assigned to Xilinx, Inc. These U.S. Patents are incorporated by reference as setting forth detailed descriptions of the programmable gate array architecture and implementations of the same.
In brief, a field-programmable gate array device can be characterized as a monolithic integrated circuit having four major architectural features: (1) a user-configurable memory means (SRAM, EEPROM, anti-fuse, or other) for storing user-provided configuration instructions; (2) a plurality of Input/Output Blocks (IOB's) for interconnecting internal circuits of the FPGA device with external circuitry and/or with other IOB's of the FPGA device and/or with other internal circuit components of the FPGA device; (3) a plurality of Configurable Logic Blocks (CLB's) for carrying out user-programmed logic functions that are stored within the user-configurable memory means; and (4) a Configurable Interconnect Network (CIN) for routing signals within the FPGA device between the IOB's and the CLB's in accordance with user-programmed routing instructions that are also stored within the user-configurable memory means.
The CIN (Configurable Interconnect Network) of an FPGA device is itself divisible into two or more major architectural subdivisions which may be categorized as: (4a) a General Interconnect Network (GIN) which provides signal routing paths between any CLB and any other CLB or IOB by way of a gridwork of short-haul conductors and switching matrix blocks interposed at intersections of the gridwork; (4b) a Longline Interconnect Network (LIN) which provides signal routing paths between select groups of CLB's by way of one or more long-haul conductors placed adjacent to the CLB's of each select group; and (4c) a Direct Interconnect Network (DIN) which provides signal routing paths between immediately adjacent CLB's.
One shortcoming of a General Interconnect Network (GIN) is that it usually adds substantial delay to the propagation of signals carried over its user-configured routing paths. The amount of delay varies with the number of switching matrix blocks and the number of short-haul conductors used to route a signal between various circuit points. Each switching matrix block of the GIN includes at least one, and usually more, programmable switches (e.g., field-effect pass transistors) which add capacitance to the GIN routing path and thereby increases its signal propagation time.
The Longline Interconnect Network (LIN) is included in most designs for the purpose of overcoming the slow propagation times of the GIN. If the gridwork of short-haul conductors in the GIN is analogized to local streets in a city, with the switching matrix blocks of the GIN acting as speed-reducing stop signs at every street corner, the LIN can be analogized to a high speed freeway which can carry signals much more quickly across town (e.g., from one side of the integrated circuit chip to an opposed side).
The problem with a Longline Interconnect Network (LIN), however, is that it provides a relatively limited amount of signal routing. Practical considerations constrain the number of long-haul conductors that may be provided on the finite surface area of an FPGA device. The number, and positioning of long-haul conductors (longlines) has to be selected judiciously. Also, the number of, and distance between, signal entry/exit points on each long-haul conductor (each longline) need to be chosen carefully. If too many signal entry/exit points are provided on a given longline, the signal propagation speed of the longline will suffer because each signal entry/exit point adds more capacitance to the longline. If signal entry/exit points are positioned in the wrong places relative to adjacent CLB's of the longline, it may not be possible to couple a desired signal from one CLB to the longline and to speed the transmission of the signal to a distant other CLB within a required time span.
The above considerations have resulted in limited use of the Longline Interconnect Network (LIN) of FPGA's.
3b. Board Level Rerouting of Bus Signals
One of the truly advantageous features of static-RAM based, user-programmable devices (UPD's) such as the Xilinx or AT&T or Altera FPGA devices is that their internal signal routing paths and/or logic functions can be conveniently changed with each engineering re-design. One simply introduces new configuration data into the user-configurable memory means (SRAM).
The same is unfortunately not true for printed circuit boards, especially the multi-layer kind. If the edge connections of a printed circuit board (PCB) have already been specified, and the positionings (placement) on the PCB of various integrated circuit chips (IC's) have been chosen, and moreover, the pinouts of the IC's have been defined, and the layout for traces interconnecting specific pins of the IC's have also been designed; it is very difficult and expensive at that point in the design process to make major revisions, at the board-level, to the design of the on-board circuit. This is particularly so in modern, high-frequency designs where the time for signal propagation through board-level interconnect is critical and special attention has to be paid to the timing relationships of time-parallel pulses that travel side-by-side in multi-line buses.
It is not uncommon to find situations where an engineering re-design is requested and the re-design calls for a change in bus routing between IC chips. An on-board multi-line bus that ran to subcircuit A may have to be rerouted to subcircuit B. This can create major difficulties if printed circuit boards have already been designed and mass-produced. A re-design might disadvantageously require the discard of already produced boards and a manufacture of a large batch of new boards.